Hardware

AVX2

2013ActivePublished: 9 November 2026Updated: 9 November 2026Published

Key innovation

Expands most vector-integer operations from 128 to 256 bits (YMM registers) and adds gather operations, which together with FMA3 enable more multiply-accumulate operations per cycle and accelerate ML inference on CPU without dedicated hardware.

How it works

AVX2 operates on sixteen 256-bit YMM registers (in x86-64 mode), each holding e.g. 8 float32, 4 float64 or 32 int8 values. Unlike AVX, which limited integer operations to 128 bits, AVX2 extends most vector-integer instructions to the full 256 bits. The gather instruction loads vector elements from non-contiguous memory addresses (indexing by a vector of offsets), simplifying the vectorization of sparse accesses. DWORD/QWORD permutes and variable vector shifts add data-processing flexibility. The co-introduced FMA3 fuses a multiply and an add into one three-operand instruction (a ← a + b·c), doubling effective floating-point throughput. In ML kernels, integer dot products are built from instructions such as VPMADDWD, which multiply pairs of 16-bit words and horizontally accumulate into 32-bit values — a core building block of quantized GEMM in libraries like llama.cpp.

Problem solved

Numerical compute and ML model inference on CPU are limited by vector-unit throughput. AVX2 doubles the width of integer vectors (256 vs 128 bits), adds gather for efficient access to non-contiguous data and — together with FMA3 — multiply-accumulate in a single cycle, accelerating GEMM, dot products and neural-network layers without a dedicated accelerator.

Components

YMM registersVector operand storage

Sixteen 256-bit vector registers (in x86-64 mode) holding e.g. 8× float32, 4× float64 or 32× int8; extension of the XMM/AVX registers to full integer-operation support.

256-bit integer operationsIncreased integer-operation throughput

Extension of most vector-integer SSE/AVX instructions from 128 to 256 bits — the key AVX2 change over AVX (which stayed 128-bit for integers).

FMA3 (fused multiply-add)Single-cycle floating-point multiply-accumulate

Three-operand fused multiply-add (a ← a + b·c) in a single instruction. Formally a separate extension with its own CPUID flag, introduced by Intel in the same Haswell microarchitecture and usually considered together with AVX2.

Official

Gather instructionsVectorized access to scattered data

Loads vector elements from non-contiguous memory locations based on a vector of offsets — simplifies vectorization of sparse or indexed data accesses.

Permutes and vector shiftsReorganizing and scaling data within a vector

DWORD/QWORD-granularity any-to-any permutes and variable-count vector shifts — flexible shuffling and scaling of elements within a register.

VPMADDWDInteger dot-product primitive

Instruction that multiplies pairs of signed 16-bit words and horizontally accumulates into 32-bit values; in its VEX.256 (AVX2) form it is a core building block of integer dot products and quantized GEMM in ML inference kernels.

Evolution

Original paper · 2013 · Intel Corporation

Intel Architecture Instruction Set Extensions Programming Reference (AVX2)

2011

Predecessor — AVX (Sandy Bridge)

Intel introduces AVX in the Sandy Bridge microarchitecture (Q1 2011): 256-bit YMM registers and VEX encoding, but integer operations remain 128-bit.

2013

AVX2 launch — Haswell

Inflection point

Intel introduces AVX2 ("Haswell New Instructions", Q2 2013): integer operations extended to 256 bits, gather, permutes and vector shifts; FMA3 appears in the same microarchitecture.

2015

AMD support — Excavator

Inflection point

AMD adds AVX2 support in the Excavator microarchitecture (Q2 2015), and subsequently in the Zen family.

2016

Successor — AVX-512 (Knights Landing)

The first hardware implementation of AVX-512 (proposed by Intel in July 2013) widens SIMD vectors to 512 bits, succeeding AVX2.

AVX-512 (concept)

2020

AVX2 in Celeron/Pentium brands — Tiger Lake

Celeron- and Pentium-branded processors start supporting AVX2 from Tiger Lake (Q3 2020), completing the extension's broad availability across Intel CPUs.