PCIe Gen6
How it works
1) PAM4 modulation: instead of two voltage levels (0/1) the signal uses four levels, encoding 2 bits per symbol; at the same symbol rate as PCIe 5.0 this doubles the data rate to 64 GT/s per lane. 2) FLIT encoding: data is transmitted in fixed-size Flow Control Units, which simplifies link-layer handling and is a prerequisite for error correction. 3) FEC + CRC: a lightweight, low-latency forward error correction (described in the literature as 3-way interlaced) together with CRC corrects errors introduced by the more sensitive PAM4 signaling, avoiding costly retransmissions. 4) Lane scaling: throughput scales linearly with link width (x1, x4, x8, x16). 5) Backward compatibility: devices negotiate the lowest common generation, so PCIe 6.0 interoperates with older hardware.
Problem solved
The bandwidth demands of AI accelerators, GPUs, memory and networking in data centers rapidly exhaust PCIe 5.0's capacity, while pushing NRZ signaling frequencies higher runs into physical limits (channel loss and noise). PCIe 6.0 addresses this by doubling the per-lane data rate at the same Nyquist frequency through PAM4, while preserving signal integrity via FLIT framing and FEC.
Components
Four-level pulse-amplitude modulation encoding 2 bits per symbol. Replaces two-level NRZ and doubles the data rate without increasing the Nyquist frequency.
Transmission of data in fixed-size Flow Control Units. Simplifies the link layer and enables the use of FEC.
Lightweight, low-latency forward error correction (described as 3-way interlaced) working with CRC. Compensates for PAM4's higher noise sensitivity without costly retransmissions.
Evolution
First generation: 2.5 GT/s per lane, 8b/10b encoding.
5 GT/s per lane.
8 GT/s per lane, switch to 128b/130b encoding.
16 GT/s per lane.
32 GT/s per lane.
64 GT/s per lane; introduction of PAM4, FLIT and FEC with CRC. PCI-SIG, 11 January 2022.
CXL 3.0 (2 August 2022) is based on the PCIe 6.0 physical layer and PAM4, doubling bandwidth over CXL 2.0.
128 GT/s per lane; announced June 2022, finalized June 2025.
Hyperparameters (configurable axes)
Number of parallel lanes (x1, x4, x8, x16). Throughput scales linearly with link width.
Raw data rate of a single lane. In PCIe 6.0 this is 64 GT/s (double PCIe 5.0).
Hardware requirements
PCIe 6.0 is a general-purpose I/O bus connecting any device (GPU, CPU, NIC, storage, accelerators) regardless of its architecture.
The doubled host-to-GPU bandwidth is especially relevant for AI accelerators in data centers.