Tape-out
How it works
Tapeout caps the design flow: (1) logic design in RTL (Verilog/VHDL) and synthesis into a gate netlist; (2) physical design โ floorplanning, placement, routing, clock-tree insertion; (3) signoff โ design-rule checking (DRC), layout-versus-schematic (LVS), static timing analysis (STA), power, signal integrity, and reliability; (4) generating the final layout in GDSII/OASIS and mask data prep. Once approved, the data is handed to the foundry (the actual tapeout). The foundry prepares masks (with optical proximity correction, OPC) and fabricates the first wafers. The resulting "first silicon" is tested for function and performance; any bugs lead to a respin โ fixing the design and another tapeout (a full one, or a metal respin limited to interconnect layers). The full cycle from tapeout to working samples usually takes weeks to months.
Problem solved
Manufacturing an IC requires physical masks that are very expensive and slow to produce, and once made the design can no longer change. Tapeout formalizes the moment of "freezing" the design โ a clear checkpoint after which everything must be verified (signoff), because the cost of a bug rises sharply. This focuses teams on verification before the irreversible manufacturing step.
Components
The final file with the geometry of all chip layers, handed to the foundry as the basis for making the photomasks.
The set of pre-tapeout checks: design rules (DRC), layout-versus-schematic (LVS), static timing (STA), power, and reliability.
The physical masks the foundry makes from the tapeout data; their cost (part of NRE) rises sharply with node advancement.
The first fabricated chip samples, tested for function and performance; discovered bugs lead to a respin.
Implementation
A bug found only in first silicon requires a new tapeout and mask set โ months of delay and millions in cost.
Skipped or unfinished design-rule and layout-versus-schematic checks can lead to faulty masks.
Foundry production windows, mask queues, and fab cycle time can slip the launch even with a finished design.
Evolution
Final chip data was loaded onto paper tape, later magnetic tape, shipped to the fab โ hence "tape-out."
The GDSII format (Calma) becomes the de facto standard for exchanging mask geometry between design and fab.
SEMI introduces the OASIS format, greatly reducing layout file size as chip complexity grows.
With the AI-accelerator boom (GPU/TPU/NPU), tapeout becomes a key, publicly communicated milestone in hardware launch schedules.
Hyperparameters (configurable axes)
The foundry process node (e.g., 5 nm, 3 nm) determines design rules, mask cost, and the tapeout schedule.
The scope of a post-first-silicon fix: a full respin (all masks) vs. a metal respin (interconnect layers only) โ different cost and time.
The mask-data format; OASIS is newer and more compact than the long-standing GDSII standard.
Execution paradigm
Hardware requirements
Tapeout is a manufacturing-process stage for any integrated circuit (CPU, GPU, TPU, NPU, FPGA-ASIC) โ independent of the target logic type.
An FPGA needs no tapeout of its own (it is configured by bitstream), but the FPGA chip itself was earlier created via a tapeout at the vendor.