AI designed an inference chip in two weeks. Now it must prove it

Architect Labs says its AI system designed the Redwood inference accelerator from specification to a working FPGA implementation in under two weeks, with no human input below spec level. VentureBeat reported it on September 18, 2026. Redwood does not exist in silicon yet, and its production figures are projections.

Key takeaways

From specification to bug-free RTL on FPGA in under two weeks
95% code and functional coverage in every block, no verification engineers
Redwood Nano on FPGA: 12.1 tokens per second at 250 MHz running Qwen3 0.6B
Projection for Samsung 8 nm: 49 tokens/s at 1.335 W vs 28 tokens/s at 2.59 W for Jetson Orin Nano

A loop instead of a toolchain

The Architect Labs platform ran the whole flow: performance modeling, RTL generation, testing, verification, firmware and kernelsKernel: An optimized compute routine that runs on the accelerator and implements an operation such as matrix multiplication.. The first RTL sent to FPGA had no bugs, the company says, and a spec change yielded a new verified design in under 48 hours. Optimization runs fell from 15 hours to 15–30 minutes.

Human

Specification

Architect Labs AI loop

Performance modeling

RTL generation

Testing and verification

Firmware and kernels

FPGA prototypeAllow

Tapeout at TSMC

The opportunity for AI in hardware design is not task acceleration within existing flows but the reimagining of the entire flow itself.

Architect Labs researchers, quoted by VentureBeat.

FPGA numbers, silicon promises

Right now Redwood loses: 12.1 tokens per second on FPGA against a measured 28 on the Jetson Orin Nano. The advantage appears only after tapeout: the company projects 49 tokens per second at 1.335 W against the rival’s 2.59 W, a 3.4× better performance-per-watt ratio from a 2.88 mm² NPU block. Projection, not measurement.

Metric	Redwood (projected, Samsung 8 nm)	NVIDIA Jetson Orin Nano (measured)
Throughput	49 tokens/s	28 tokens/s
Power draw	1.335 W	2.59 W
Performance per watt	approx. 36.7 tokens/s/W	approx. 10.8 tokens/s/W

\dots ▶ Symbol meaning \dots performance per watt, meaning tokens per second delivered per watt \dots throughput in tokens per second \dots power draw in watts

3.4×better performance per watt than the Jetson Orin Nano (silicon projection)Architect Labs

OpenAI took a different route

IEEE Spectrum described on September 14 how OpenAI used its own models on the Jalapeño chip: AI converted high-level code to Verilog and cut matrix multiplication unit area by 10%, but humans ran the project and RTL to tapeout took nine months. OpenAI speeds up the existing flow. Architect Labs wants to replace it.

Why it matters

The semiconductor industry measures progress in tapeouts, not demonstrations. If automated verification holds quality at first silicon, it changes not only the pace but the barrier to entry: an accelerator would no longer need a hundred-person team. The risk is symmetrical. A system that writes and grades its own tests can carry blind spots that surface only when the chip returns from the fab.

Caveat: Redwood exists today only as an FPGA prototype. The figures for the Samsung 8 nm process are a calibrated projection, not a measurement. There is no silicon yet, so only tapeout will settle it.

What’s next

Redwood tapeout at TSMC. Only silicon will validate the FPGA projections, and no date has been given.
In 2024 only 14% of IC/ASIC projects hit working silicon on the first attempt, the lowest rate in 20 years.
The first Jalapeño chips returned from the fab in May 2026, a reference point for OpenAI’s pace.