NVIDIA Holoscan Sensor Bridge is a hardware-software platform designed for low-latency acquisition of high-bandwidth sensor data and direct delivery to GPU memory over Ethernet. It is a key component of the NVIDIA Holoscan ecosystem โ the platform for AI sensor data processing in medical, robotics, and industrial applications.
The platform consists of three layers. First, a physical FPGA-based hardware device (Lattice CertusPro-NX or Microchip PolarFire MPF200) receives sensor data via a native sensor interface (MIPI CSI-2, AXI Stream, CoaXPress). Second, the FPGA packetizes the data into UDP frames and sends them over a 2x 10 GbE link to the host. Third, on the host, a ConnectX NIC writes data directly into GPU memory via GPUDirect RDMA โ without CPU involvement โ minimizing end-to-end latency.
Lattice CertusPro-NX Sensor to Ethernet Bridge Board (LF-SNSR-ETH-EVN) โ first certified reference implementation. Lattice CertusPro-NX FPGA, 2x 10GbE (RJ45 + SFP+), MIPI CSI-2 and AXI Stream interfaces. Available through Arrow and Digi-Key.
Microchip PolarFire MPF200 Ethernet Sensor Bridge โ implementation based on Microchip PolarFire FPGA (MPF200). Supports the same interfaces and API as the Lattice implementation.
Source code published on GitHub (nvidia-holoscan/holoscan-sensor-bridge) under Apache 2.0 license. The package provides: a streaming operator compatible with the Holoscan SDK (C++ and Python), SIPL/UDDF drivers for camera support, HSB Emulator module (for testing without physical hardware), GPUDirect RDMA support via RoCE (RDMA over Converged Ethernet) with Linux sockets as fallback. Integration with the Holoscan SDK enables building complete end-to-end AI pipelines from sensor to inference result.
Applications: medical imaging (endoscopy, robotic surgery, ultrasound, tomography), industrial inspection, robotics with real-time sensor fusion, edge AI. Certified integration partners: Lattice Semiconductor, Microchip Technology, Leopard Imaging (IMX274/VB1940 Eagle cameras), e-con Systems, Analog Devices (GMSL), Yuan and Deltacast (IO capture cards for Holoscan). Surgical robotics adoption: Virtual Incision (next-generation robotic surgical platform with Holoscan Sensor Bridge).
FPGA Ethernet Sensor Bridge ยท serves as: Sensor Data Ingestion, Sensing, Communication, Perception. ยท compatible with: Medical Robot, Industrial Robot, Humanoid, Robotic Arm.
Which group NVIDIA Holoscan Sensor Bridge belongs to and how it is built
FPGA-based hardware boards and modules designed for low-latency streaming of sensor data to CPU/GPU over Ethernet or other high-speed interfaces.
A class of FPGA-based hardware devices that receive data from sensors (MIPI cameras, ultrasound, industrial sensors) via the sensor-native interface, then packetize it into UDP frames and transmit over a high-speed Ethernet link (10/25/100 GbE) to a host equipped with a ConnectX NIC. On the host, data lands directly in GPU memory using GPUDirect RDMA (bypassing CPU copy), minimizing end-to-end latency from sensor to AI algorithm. Examples: NVIDIA Holoscan Sensor Bridge (Lattice CertusPro-NX), Microchip Ethernet Sensor Bridge (PolarFire MPF200). Common in medical robotics, industrial inspection, and edge AI.
Design pattern distinguished by: (1) Sensor input via native sensor interface (MIPI CSI-2, CoaXPress, GigE Vision, AXI Stream). (2) FPGA handles: sync, prebuffering, UDP packetization, precise timestamping (PTP/IEEE 1588). (3) Output via high-speed Ethernet (10G, 25G) to a ConnectX NIC with RDMA support. (4) Data lands in GPU memory via GPUDirect RDMA without CPU involvement โ sub-ms end-to-end latency. (5) Software layer: standard API with transport abstraction, SIPL/UDDF drivers, streaming operator compatible with SDK (e.g., Holoscan SDK). Commercially realized as: Lattice CertusPro-NX Sensor Bridge, Microchip PolarFire Ethernet Sensor Bridge.
Input: sensor interface (AXI Stream) + APB control. Output: Ethernet (UDP). Internally: Dataplane, Peripheral Interface, Register Interface, PTP.
edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/hsb/fpga_ip/
SystemVerilog 30%, Verilog 5%, C++ 36%, Python 21%, CUDA 2% (per GitHub 2026)
SystemVerilog 30%, Verilog 5%, C++ 36%, Python 21%, CUDA 2% (per GitHub 2026)
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