Subcategory of integrated SoC designs targeting AI inference, computer vision, and embedded edge computing workloads.
Covers integrated System-on-Chip circuits used as central processing units in embedded systems, robotics, AIoT, and edge AI devices. In this schema, parentCategory is set to 'other' because the parentCategory enum does not include a compute category.
AMD Ryzen AI Embedded P100 is an edge SoC with Zen 5/5c CPU (up to 12 cores), RDNA 3.5 GPU, and XDNA 2 NPU — up to 50 TOPS on NPU, 80 TOPS combined, for mobile robotics 2025+.
Apple SoC from September 2017 (iPhone 8, 8 Plus, iPhone X), 10 nm TSMC, 4.3 billion transistors, 6 ARMv8.2-A cores. First Apple chip with a dedicated Neural Engine (600 billion ops/s) powering Face ID and Animoji. Discontinued in 2020.
Apple-announced server chip planned for H1 2027, supporting up to 1.5 TB of RAM. Descended from the architecture built for the discontinued Project Titan. Apple is skipping M6 Pro/Max/Ultra variants to speed up its debut.
Apple's series of AI accelerators (NPU), integrated as a block in A- and M-series SoCs since 2017. M4 reaches 38 TOPS; an expanded version is announced in the M7 Ultra server chip for 2027.
13 TOPS M.2 AI accelerator drawing only 1.5 W with no external DRAM — designed for Raspberry Pi AI HAT+.
