Subcategory covering dedicated AI accelerators (ASIC, GPU, XPU) designed for data-center-scale operation — training and inference of large foundation models, recommendation and generative systems. The opposite of edge-AI SoCs.
This subcategory groups integrated circuits designed to accelerate AI computation in data centers: NVIDIA H100/B200, Google TPU, AWS Trainium/Inferentia, Meta MTIA, Groq LPU, Cerebras WSE. Common properties: high-bandwidth HBM memory, low-precision modes (FP16/BF16/FP8/MX8/MX4/INT8/INT4), scalability to rack-scale (hundreds of chips in a single scale-up domain), liquid cooling, integration with ML frameworks (PyTorch, JAX, Triton, vLLM). This contrasts with hardwareSubcategory.ai-soc-edge-ai-soc where the criteria are the opposite (low power, no HBM, on-device inference).
Cerebras' world-largest AI processor — an entire silicon wafer as a single chip. WSE-3 (2024): 4T transistors, 900,000 cores, 125 PFLOPS.
IBM's dedicated AI accelerator system-on-a-chip on a PCIe card for generative and agentic AI inference on IBM Z (z17), LinuxONE 5 mainframes and Power11 servers.
Meta's family of homegrown AI chips (6 generations: 100, 200, 300, 400, 450, 500) developed with Broadcom. Chiplet architecture, ~6-month cadence, PyTorch-native, hundreds of thousands of chips in production.
NVIDIA Hopper is a data-center GPU architecture (2022) named after Grace Hopper. It introduced the Transformer Engine and FP8 precision; it powers the H100, H200 and GH200 Grace Hopper accelerators. Predecessor to the Blackwell architecture.
The TPU (Tensor Processing Unit) is Google's custom AI accelerator (ASIC) for machine learning, based on a systolic-array architecture (MXU, bfloat16). Available on Google Cloud; used e.g. to train the Gemini models.
