FPGA
How it works
The designer describes the circuit in HDL (Verilog/VHDL) or in C/C++ via High-Level Synthesis. Tools (e.g., AMD Vivado, Intel Quartus) perform: logic synthesis (description → a netlist of gates/LUTs), then implementation — mapping onto available CLBs, placement, and routing of interconnect, with timing analysis meeting clock constraints. The output is a bitstream — a configuration file that sets each LUT's contents, flip-flop states, and interconnect switches. The bitstream is loaded into configuration cells (usually SRAM, which is volatile — reloaded at each power-up from external flash). Once configured, the FPGA acts as a dedicated, massively parallel circuit: many operations run simultaneously in space (dataflow), and the data pipeline flows through the logic on every clock cycle. For AI, network layers are mapped onto DSP slices and on-chip memory, often with quantization to low precision (INT8/INT4/bfloat16) for maximum throughput.
Problem solved
An ASIC offers maximum performance, but designing and fabricating one takes months to years and costs millions, and it cannot be changed once made. A general-purpose CPU is flexible but inefficient and power-hungry for highly parallel, fixed computations. The FPGA fills the gap: it delivers hardware parallelism and low latency while remaining reprogrammable — ideal for rapidly evolving algorithms such as AI models.
Components
The basic FPGA logic unit, containing lookup tables (LUTs), flip-flops, and multiplexers. Configuring the LUTs realizes any logic function of a few inputs.
A network of configurable wires and switches connecting logic blocks, memories, and I/O. It gives the FPGA its topological flexibility and is often the latency bottleneck.
Hard multiply-accumulate (MAC) blocks, key for signal processing and matrix multiplication in neural networks. Their count sets the peak compute throughput.
Distributed blocks of fast on-chip memory used to buffer data, weights, and intermediate results — avoiding costly off-chip memory access.
Programmable edge interfaces supporting various electrical standards and high-speed serial transceivers (e.g., PCIe, Ethernet).
Implementation
Reaching the target clock frequency while meeting timing constraints is hard at high utilization and with long critical paths.
On-chip memory (BRAM) is limited; AI models often need careful buffering and streaming of weights from external memory.
Synthesis, placement, and routing of large designs take hours, and hardware debugging is harder than in software.
Evolution
Xilinx (Ross Freeman) introduces the XC2064 with programmable gates and interconnect — the birth of the FPGA category.
LUT-based architectures and Verilog/VHDL design flows make FPGAs a standard for prototyping and signal processing.
Devices combining FPGA fabric with hard processors (e.g., Xilinx Zynq) emerge, uniting software control with hardware acceleration.
Microsoft deploys FPGAs to accelerate Bing search, kicking off a wave of FPGA use in AI and network acceleration (later Brainwave/Azure).
AMD acquires Xilinx (2022); Intel had acquired Altera (2015, spun off 2024). FPGAs integrate with CPU/GPU platforms as heterogeneous accelerators.
Hyperparameters (configurable axes)
The number of available LUTs and flip-flops — determines how large and complex a design can fit.
The number of MAC blocks — directly caps peak multiply throughput for neural networks.
The achievable post-routing clock frequency — depends on critical-path length; sets pipeline throughput.
Post-quantization arithmetic precision — lower precision increases parallel MACs and throughput at the cost of accuracy.
Execution paradigm
Parallelism
An FPGA offers spatial parallelism: hundreds to thousands of operations run simultaneously in a dataflow pipeline rather than sequentially as on a CPU.
Hardware requirements
The FPGA is this very hardware type — the concept describes reprogrammable logic fabric as the compute substrate.
FPGA designs (RTL/HLS) can be partly retargeted to ASIC or emulated, though performance and characteristics differ.