Tooling

Verilog

ActivePublished: 20 September 2026Updated: 20 September 2026Published

Key innovation

A C-like hardware description language that let engineers describe, simulate, and (once synthesis arrived) automatically realize digital circuits at the RTL level — turning hardware design into a scalable, text-based process.

How it works

The designer writes Verilog modules describing the circuit's structure and behavior. Combinational logic is expressed via assign or always @(*) blocks; sequential logic via always @(posedge clk) with non-blocking assignments (<=). The code is event-driven and concurrent — many always blocks run in parallel. A simulator (e.g., event-driven Icarus/ModelSim or cycle-based Verilator) runs a testbench that applies stimuli and checks responses. For fabrication, a synthesis tool (e.g., Yosys, Design Compiler) translates the synthesizable Verilog subset into a gate netlist, then mapped onto ASIC cells or FPGA resources. Key rules: use non-blocking assignments in sequential logic and blocking in combinational, write complete assignments (avoid unintended latches), and stay within the synthesizable language subset.

Problem solved

Rising IC complexity made schematic and gate-level design impractical. Verilog provided a text-based, hierarchical, simulatable, and synthesizable way to describe hardware at a high level (RTL), enabling pre-fabrication verification and automation of the path from description to finished circuit.

Components

ModuleHierarchical organization of the design

The basic unit of Verilog description: a block with input/output ports, composed hierarchically into larger circuits.

Procedural blocks (always/initial)Describing behavior over time

always blocks (combinational/sequential logic) and initial blocks (initialization/testbench) triggered by events, e.g., a clock edge.

Nets and variables (wire/reg)Representing connections and state

Signal types: wire (continuously driven, connects elements) and reg (holds a value between procedural assignments).

Assignments (blocking/non-blocking)Signal-update semantics

Blocking (=) assignments model immediate (combinational) computation; non-blocking (<=) model simultaneous register updates on the clock edge.

Implementation

Reference implementations

Icarus Verilog

C/C++ · Stephen Williams (open source)

Verilator

C++ · Veripool

Implementation pitfalls

Blocking vs non-blocking assignmentsHigh

Using = instead of <= in sequential logic (or vice versa) causes simulation–synthesis mismatches and race conditions.

Fix:Follow the rule: <= for sequential, = for combinational.

Non-synthesizable constructsMedium

Delays (#), unbounded loops, and some testbench constructs work in simulation but are not synthesizable.

Fix:Separate synthesizable code from testbench; stay within the synthesizable subset.

Incomplete sensitivity lists / latchesMedium

An incomplete sensitivity list or missing else leads to simulation mismatch and inference of unintended latches.

Fix:Use always @(*), complete assignments, and default values.

Evolution

Original paper · 1984 · Gateway Design Automation (1983–1984) · Prabhu Goel

Verilog HDL — Gateway Design Automation

Prabhu Goel, Phil Moorby, Chi-Lai Huang

1984

Verilog created (Gateway Design Automation)

Inflection point

Prabhu Goel, Phil Moorby, and Chi-Lai Huang create Verilog as a hardware description and simulation language; the name combines "verification" and "logic."

1990

Cadence acquisition

Cadence Design Systems acquires Gateway; Verilog is soon opened publicly (Open Verilog International), accelerating adoption.

1995

IEEE 1364-1995 standardization

Inflection point

Verilog becomes an open IEEE standard, alongside later 2001 (signed arithmetic) and 2005 revisions.

2009

Merged into SystemVerilog (IEEE 1800)

IEEE 1364-2005 is merged into the SystemVerilog standard (IEEE 1800-2009), adding advanced verification and object-oriented constructs.