SVE
How it works
SVE does not hard-code the vector length into instructions. Instead, operations act on Z registers whose width is fixed only in hardware (128–2048 bits), and loop control relies on P predicate registers: a predicate selects which vector lanes are active in a given iteration, handling loop remainders and conditionals without separate scalar code. Instructions such as WHILELT build a predicate from the current index and the loop bound, while INCB/CNTB advance a counter by the (compile-time-unknown) vector length. SVE also provides gather-load / scatter-store for scattered addresses and an FFR (First Fault Register) that enables speculative, fault-tolerant loads — key to vectorising loops of unknown length. Compilers (GCC, LLVM/Clang) emit SVE via auto-vectorisation, or developers use C intrinsics; the same binary uses the full register width of a given CPU. SVE2 (Armv9-A) broadens the set with DSP and general-purpose instructions.
Problem solved
Traditional SIMD extensions (NEON, AVX) use a fixed vector width, so code tuned for one width must be rewritten or recompiled for another and does not automatically benefit from wider units. This hurts portability across CPUs of differing performance — from mobile devices to HPC. SVE solves this with a vector-length-agnostic model: a single binary runs correctly and scales across implementations of 128–2048 bits, without tying software to a specific register width.
Components
A model in which the vector length is not encoded in instructions. The implementer picks a hardware register width in the 128–2048-bit range in multiples of 128, and SVE code runs correctly on any of them without recompilation.
32 scalable vector registers whose width is fixed in hardware (128–2048 bits). The low 128 bits of each Z register overlap the corresponding V (NEON) register.
16 predicate registers that mask individual vector lanes; P0–P7 act as governing predicates for load/store and arithmetic. They enable per-lane predication and loop control without separate scalar code.
Vector load/store instructions to and from scattered, non-contiguous memory addresses given by a vector of indices or offsets.
The successor to SVE introduced with the Armv9-A architecture (2021), broadening the instruction set with DSP, media and general-purpose operations while keeping the VLA model.
Implementation
Evolution
ARM (with Fujitsu, targeting the Japanese post-K supercomputer) announces SVE — a scalable SIMD vector extension for HPC, complementary to NEON.
The Fujitsu A64FX with 512-bit SVE powers the Fugaku supercomputer, the fastest in the world from June 2020 to May 2022.
The Armv9-A architecture mainstreams SVE2, broadening the instruction set with DSP, media and general-purpose operations beyond the HPC niche.
The AWS Graviton3 CPU implements a flexible 2×256-bit SVE variant, bringing scalable vectors to ARM server CPUs in the cloud.
Hyperparameters (configurable axes)
The hardware width of the Z vector register, chosen by the implementer in the 128–2048-bit range in multiples of 128. It is invisible to the code (VLA) but determines throughput on a given CPU.
Execution paradigm
SIMD applies the same operation across all vector lanes, but the P predicate registers mask individual lanes depending on loop bounds and conditions (per-lane predication).
Parallelism
Data parallelism within a single scalable-length vector instruction; used in both scientific computing (HPC) and ML inference.
Hardware requirements
SVE is the native, scalable SIMD extension of ARM/AArch64 CPUs (Fujitsu A64FX, AWS Graviton3, Neoverse cores, mobile and edge SoCs). A "CPU SIMD" category — the scalable ARM counterpart of x86 AVX.