The TPU (Tensor Processing Unit) is a family of dedicated ASICs designed by Google to accelerate neural-network computation. At the heart of a TPU is a systolic array with a matrix-multiply unit (MXU), support for the bfloat16 format (developed by Google Brain) and high-bandwidth memory. This architecture is optimized for the massive matrix-multiplication operations that dominate AI training and inference.
Google began using TPUs internally in 2015, publicly announced them at Google I/O in May 2016, and has offered them to external users via Google Cloud (Cloud TPU) since 2018. Successive generations: v1 (2015, inference), v2 (2017, training), v3 (2018), v4 (2021, up to 275 TOPS/chip, pods of up to 4,096 chips), v5e and v5p (2023), v6e 'Trillium' (2024), v7 'Ironwood' (2025) and v8 (2026). Chips are combined into pods of thousands, with a fast inter-chip network (optical circuit switching from v4 onward).
TPUs powered AlphaGo and AlphaZero, text processing in Google Street View, Google Photos and the RankBrain search-ranking system, as well as the training of Google's flagship models, including the Gemini family. In software, TPUs mainly support JAX, TensorFlow and PyTorch/XLA.
AI Accelerator · serves as: AI acceleration, AI Inference, Compute.
Which group TPU belongs to and how it is built
This subcategory groups integrated circuits designed to accelerate AI computation in data centers: NVIDIA H100/B200, Google TPU, AWS Trainium/Inferentia, Meta MTIA, Groq LPU, Cerebras WSE. Common properties: high-bandwidth HBM memory, low-precision modes (FP16/BF16/FP8/MX8/MX4/INT8/INT4), scalability to rack-scale (hundreds of chips in a single scale-up domain), liquid cooling, integration with ML frameworks (PyTorch, JAX, Triton, vLLM). This contrasts with hardwareSubcategory.ai-soc-edge-ai-soc where the criteria are the opposite (low power, no HBM, on-device inference).
An AI Accelerator is a specialized hardware component designed for efficient execution of artificial intelligence computations, particularly neural network inference, computer vision processing, and sensor data analysis. In robotics, AI accelerators are used to run perception models, object recognition, image segmentation, planning, and other tasks that require high computational throughput under constrained power budgets. They may take the form of dedicated NPU, TPU, VPU, or GPU chips, or specialized embedded modules.
A data-center AI accelerator card is a design class describing the construction of high-performance compute processors (GPUs/accelerators) intended for mounting in data-center servers. It is characterised by: an SXM form factor (a module soldered onto an HGX/DGX baseboard) or a dual-slot PCIe card; high-bandwidth memory (HBM2e/HBM3/HBM3e) integrated on-package; dedicated GPU-to-GPU interconnects (NVLink, Infinity Fabric) with hundreds of GB/s of bandwidth; high TDP (350–1000 W) requiring air or liquid cooling; support for virtualisation/partitioning (MIG) and low-precision compute formats (FP8/FP16/BF16/INT8). The class includes designs such as NVIDIA H100/H200/A100, AMD Instinct MI300, Google TPU, and Intel Gaudi. It describes physical construction and configuration, not the functional role (which is given by the component type "AI Accelerator").
Other hardware parts related to TPU
Amazon/AWS's custom AI accelerator (ASIC) for training and inference of AI models; NeuronCore cores, HBM memory, available in EC2 (Trn) instances. Trainium3: 144 GB HBM3e and 4.9 TB/s.
NVIDIA's AI GPU architecture (2024) and the B200 chip: 208B transistors, two dies connected at 10 TB/s, TSMC 4NP, 192 GB HBM3e, 2nd-gen Transformer Engine (FP4) and 5th-gen NVLink; the basis of GB200 systems.
