AI System-on-Chip (SoC) · serves as: AI Inference, AI acceleration, Compute.
Which group IBM Spyre Accelerator belongs to and how it is built
This subcategory groups integrated circuits designed to accelerate AI computation in data centers: NVIDIA H100/B200, Google TPU, AWS Trainium/Inferentia, Meta MTIA, Groq LPU, Cerebras WSE. Common properties: high-bandwidth HBM memory, low-precision modes (FP16/BF16/FP8/MX8/MX4/INT8/INT4), scalability to rack-scale (hundreds of chips in a single scale-up domain), liquid cooling, integration with ML frameworks (PyTorch, JAX, Triton, vLLM). This contrasts with hardwareSubcategory.ai-soc-edge-ai-soc where the criteria are the opposite (low power, no HBM, on-device inference).
Component type encompassing System-on-Chip designs used as primary compute units in embedded devices, edge AI, and robotics applications.
A data-center AI accelerator card is a design class describing the construction of high-performance compute processors (GPUs/accelerators) intended for mounting in data-center servers. It is characterised by: an SXM form factor (a module soldered onto an HGX/DGX baseboard) or a dual-slot PCIe card; high-bandwidth memory (HBM2e/HBM3/HBM3e) integrated on-package; dedicated GPU-to-GPU interconnects (NVLink, Infinity Fabric) with hundreds of GB/s of bandwidth; high TDP (350–1000 W) requiring air or liquid cooling; support for virtualisation/partitioning (MIG) and low-precision compute formats (FP8/FP16/BF16/INT8). The class includes designs such as NVIDIA H100/H200/A100, AMD Instinct MI300, Google TPU, and Intel Gaudi. It describes physical construction and configuration, not the functional role (which is given by the component type "AI Accelerator").
How much power IBM Spyre Accelerator needs and how it can be powered
The IBM Spyre Accelerator is a dedicated system-on-a-chip for AI acceleration, developed by IBM Research based on the AIU (Artificial Intelligence Unit) prototype and the on-chip AI accelerator in the Telum processor. Each chip contains 32 AI accelerator cores and 25.6 billion transistors built on a Samsung 5 nm process, mounted on a 75-watt PCIe card with 128 GB of LPDDR5 memory. It supports low-precision numeric formats (int4 and int8) for energy-efficient inference and is designed to pass data directly between compute engines. Spyre targets workloads such as fraud detection, generative and agentic AI, and application modernization (including watsonx Code Assistant). Cards can be clustered: up to 48 cards in an IBM z17 system and up to 16 in a Power11 server; eight cards in a single drawer provide 1 TB of memory and 256 cores. General availability: October 28, 2025 for IBM z17 and LinuxONE 5, and early December 2025 for Power11 servers.
