Robots Atlas>ROBOTS ATLAS

Lattice CrossLink-NX

Lattice CrossLink-NX is a family of low-power FPGAs (LIFCL-17, LIFCL-33, LIFCL-40) built on the Lattice Nexus platform in 28 nm FD-SOI. It is optimized for embedded vision, MIPI camera bridging and lightweight edge AI acceleration — workloads typical for humanoid robots, mobile AMR platforms and autonomous sensor modules.

The device provides from 17k to 39k logic cells, up to two hardened MIPI D-PHY transceivers (10 Gbps per PHY, 2.5 Gbps per lane), 5 Gbps PCIe Gen2 hard IP, a 1066 Mbps DDR3 controller and programmable LVDS, subLVDS and OpenLDI I/O. In practice this enables aggregation of multiple CSI-2 cameras, image preprocessing and offloading ISP work from the main SoC.

Robotics-relevant features include instant-on configuration (I/O ready in 3 ms, device in 8 ms), a standby mode below 70 µA, the lowest soft error rate in its class (100× more reliable than competition) and AEC-Q100 automotive grade. Packages go down to a 4×4 mm WLCSP footprint, allowing integration in dense end-effector or sensor-module electronics.

In the Robocikowo catalog we treat CrossLink-NX as an industrial-class compute component used for sensor fusion, AI acceleration and visual perception — complementing main SoCs (e.g. NVIDIA Jetson, Rockchip RK3588) with deterministic, low-power sensor stream processing.

#Lattice#CrossLink-NX#LIFCL#FPGA#Edge AI#Embedded Vision#MIPI D-PHY#Sensor Fusion#Nexus Platform#Low Power
Market classIndustrial

Classification

FPGA · serves as: Sensor fusion, AI acceleration, Perception.

Which group Lattice CrossLink-NX belongs to and how it is built

4items
Compute
Hardware domain
Industrial
Market class

Programmable logic devices (FPGAs) used in robots for sensor fusion, MIPI bridging and low-power AI accelerators.

Programmable logic device used for sensor fusion and lightweight AI.

Technical specification

Basic physical properties of Lattice CrossLink-NX — dimensions, weight and materials

2parameters
Materials
Półprzewodnikowy układ scalony FPGA, proces 28 nm FD-SOI, obudowy WLCSP / QFN / csfBGA / csBGA / caBGA.
Mounting
Montaż powierzchniowy (SMT) na płycie głównej lub carrier board jako koprocesor sensor-bridging / AI.
Updated: 20 May 2026