Meta MTIA
Meta MTIA (Meta Training and Inference Accelerator) is Meta's family of homegrown AI chips developed in partnership with Broadcom. So far it covers six generations: MTIA 100 and 200 (formerly known as MTIA 1 and MTIA 2i) and the newer MTIA 300, 400, 450 and 500 — released on a roughly six-month cadence between generations. Meta has already deployed hundreds of thousands of MTIA chips in production, serving ranking-and-recommendation (R&R) and, increasingly, GenAI workloads with models such as Llama.
Six generations, one strategy
MTIA 100 and 200 — the first two generations, described in papers at ISCA, optimised for R&R inference and training (Meta's dominant workload before the GenAI era).
MTIA 300 — the foundation for subsequent generations: built-in NIC chiplets, dedicated message engines that offload collective communications, and near-memory compute for reduction. In production for R&R training; scale-out network 200 GB/s.
MTIA 400 — evolution for GenAI, a 72-accelerator scale-up domain, raw performance competitive with leading commercial products. AALC (air-assisted liquid cooling) or facility liquid cooling. Lab testing complete, en route to data centers.
MTIA 450 — a leap for GenAI inference: 2x HBM bandwidth vs 400, +75% MX4 FLOPS, hardware acceleration for Attention/FFN (Softmax, FlashAttention), low-precision data types. 6x the MX4 FLOPS of FP16/BF16. Mass deployment: early 2027.
MTIA 500 — another +50% HBM bandwidth and further low-precision innovations. Mass deployment: 2027.
Chiplet architecture
MTIA 300 consists of one compute chiplet, two network chiplets and several HBM stacks. The compute chiplet is a grid of Processing Elements (PEs) with redundancy that improves yield. Each PE contains: two RISC-V vector cores, a Dot Product Engine (matrix multiplication), a Special Function Unit (activations, elementwise), a Reduction Engine (accumulation and inter-PE communication), and a DMA engine (transfers to scratch memory). Modularity at every level — chiplet, chassis, rack, network — lets Meta upgrade individual blocks in months instead of years and manufacture different chiplets in different TSMC processes (the most cost-effective per function).
Software stack: PyTorch-native
MTIA is built natively on industry standards: PyTorch, vLLM, Triton, OCP. Seamless model onboarding via torch.compile and torch.export (eager and graph modes) with no MTIA-specific rewrites. Meta's own HCCL (Hoot Collective Communications Library) leverages the built-in network chiplets and near-memory compute. The vLLM plugin swaps key operators (FlashAttention, fused LayerNorm) for MTIA-specific kernels. Production-grade monitoring, profiling and PE-level debugger available at the scale of hundreds of thousands of chips.
Three-pillar strategy
Meta builds MTIA on three pillars: high-velocity iteration (a new chip roughly every ~6 months thanks to chiplets), inference-first focus (MTIA 450/500 optimised for GenAI inference first, then applied to other workloads) and frictionless adoption (native on industry standards). Blog authors: Yee Jiun Song, Andrew Tulloch, Harikrishna Reddy, CQ Tang, Vijay Thakkar.
Classification
Custom AI training and inference ASIC · serves as: AI acceleration, AI Inference.
Which group Meta MTIA belongs to and how it is built
This subcategory groups integrated circuits designed to accelerate AI computation in data centers: NVIDIA H100/B200, Google TPU, AWS Trainium/Inferentia, Meta MTIA, Groq LPU, Cerebras WSE. Common properties: high-bandwidth HBM memory, low-precision modes (FP16/BF16/FP8/MX8/MX4/INT8/INT4), scalability to rack-scale (hundreds of chips in a single scale-up domain), liquid cooling, integration with ML frameworks (PyTorch, JAX, Triton, vLLM). This contrasts with hardwareSubcategory.ai-soc-edge-ai-soc where the criteria are the opposite (low power, no HBM, on-device inference).
Covers Application-Specific Integrated Circuit (ASIC) chips designed inside hyperscalers (Google, Amazon, Meta, Microsoft) in partnership with semiconductor partners (Broadcom, Marvell, Alchip). Properties: modular chiplet architecture (compute, network, I/O as separate silicon blocks), HBM integration, support for low precisions (MX8/MX4, FP8), dedicated ML engines (Dot Product Engine, Attention Engine, Reduction Engine), PyTorch-native software stack. Examples: Google TPU, AWS Trainium/Inferentia, Meta MTIA, Microsoft Maia.
A construction class for AI accelerators built from separate chiplets, where each chiplet can be updated, moved to a different process node, or replaced without redesigning the whole system. Enables fast generation iteration (on the order of 6 months) and lets different chiplets be manufactured in different TSMC processes (most cost-effective per function). Examples: Meta MTIA 300-500 (compute + network chiplets + HBM stacks), AMD Instinct MI300, Intel Gaudi 3, partly NVIDIA Blackwell (dual-die).